1. Field
Exemplary embodiments relate to a recessed channel transistor and a method of manufacturing the same. More particularly, example embodiments relate to a recessed channel transistor capable of improving current performance of a dynamic random access memory (DRAM) semiconductor cell and a method of manufacturing the same.
2. Description of the Related Art
As DRAM cells are highly integrated according to a decrease in a design rule of a semiconductor device, a channel length of a MOS transistor is greatly reduced. However, a short channel effect or a punch through effect may occur frequently due to the decrease in the channel length. In order to minimize the above problems, various transistors capable of preventing the short channel effect and improving refresh characteristics have been researched. For example, a channel length of a recessed channel transistor may be increased physically without an increase in a lateral area of a gate electrode.
However, in a conventional recessed channel transistor, when a drain voltage (Vd) is applied to a capacitor that is electrically connected to a NMOS transistor, a gate induced drain leakage (GIDL) problem may occur. In order to prevent the leakage current, a predetermined negative voltage may be applied to a gate electrode of a turn-off transistor adjacent to a turn-on transistor. However, it is difficult to efficiently insulate between a gate electrode and an impurity region in a transistor having a recessed gate electrode.